1. Field of the Invention
This invention relates generally to semiconductor digital integrated circuits and more particularly to field-programmable logic array (FPLA) circuits.
2. Description of the Prior Art
Programmable integrated circuits are becoming increasingly popular in the electronics industry since they allow the manufacturer and user great flexibility in tailoring generalized circuits to meet specific applications at relatively low cost. One principal category of programmable integrated circuits is the programmable logic array of which the two basic types are the mask-programmable logic array and the FPLA. In contrast to a mask-programmable logic array which is programmed by the manufacturer from a generalized initial circuit and then distributed to the customers, an FPLA is usually distributed in an unprogrammed state to be programmed by the customer.
An FPLA conventionally employs a set of fusible links located at selected functional cross-points in the circuit. Each link is typically made of a nickel-chromium alloy. The FPLA is programmed to perform a specific function by destroying (or "blowing") a selected pattern of links so as to create open circuits at cross-point locations where no connection is desired, and to leave closed circuits at cross-point locations where the links must remain intact to provide connection.
The standard FPLA consists of a string of logical AND and OR gates arranged in a selected manner. Logical NAND and NOR gates may be utilized in conjunction with, or as substitutes for, the AND and OR gates, respectively.
Turning to the drawings, FIGS. 1A, 1B, and 1C illustrate, respectively, the internal construction of a conventional unprogrammed AND gate A suitable for an FPLA, the representation of gate A in standard notation, and the representation of gate A in a simplified notation. Referring to FIG. 1A, digital input data is provided from N lines LA1, LA2, . . . LAN to N corresponding input sections of AND gate A. More particularly, each input section comprises a Schottky diode DAJ (where J is an integer varying from one to N) connected to corresponding line LAJ. Output data from gate A is supplied from its output section on an output line OA powered by a voltage source V.sub.CC. Line OA in the output section connects to diode DAJ of each input section through a corresponding fusible link FAJ.
Utilization of AND gate A is straightforward. Before any of links FA1-FAN are blown, gate A is responsive to data on all N lines LA1-LAN. Gate A is programmed by destroying selected links FAJ to create open circuits between corresponding diodes DAJ and output line OA. This disconnects the input sections containing those diodes DAJ from the output section so that gate A is no longer responsive to data on those lines LAJ connecting to the disconnected diodes DAJ.
The representation of AND gate A in standard notation as in FIG. 1B is somewhat unsuitable to FPLA circuitry. This is alleviated by the simplified notation of FIG. 1C in which output line OA crosses each line LAJ perpendicularly. Each such intersection represents the unprogrammed coupling of line OA to line LAJ by way of fusible link FAJ and diode DAJ in the manner shown in FIG. 1A. To distinguish intersections representing connections made through unprogrammed fusible links FAJ from other intersections not intended to represent connections in FPLA circuitry, each intersection denoting a connection through fuse FAJ is marked with a small circle. After programming (not shown here), each intersection at which a link FAJ remains intact is indicated by a nodal dot while each intersection at which a link FAJ has been destroyed is indicated as an open circuit by the absence of further labeling. The AND gate symbol is placed at a suitable location along line OA to indicate the function of the illustrated circuitry.
FIGS. 2A, 2B and 2C show, respectively, the internal circuitry of a conventional unprogrammed OR gate C suitable for an FPLA, the representation of gate C in standard notation, and the representation of gate C in the simplified notation described above. Referring to FIG. 2A, N lines LC1, LC2, . . . LCN apply digital data to N corresponding input sections of OR gate C. Each input section comprises an NPN bipolar transistor QCJ having its base connected to corresponding line LCJ. Output data is provided on an output line OC in the output section of gate C. Line OC connects to the emitter of transistor QCJ in each corresponding input section through a fusible link FCJ.
OR gate C is utilized in the same manner as AND gate A. Before any of fuses FCJ are blown, OR gate C responds to data on all N lines LC1-LCN. After programming gate C by destroying selected links FCJ, the input sections previously connected to output line OC by these links FCJ are now disconnected from it, and gate C responds only to data on those ones of lines LC1-LCN coupled to the intact ones of fuses FC1-FCN.
As with AND gate A, the simplified notation of FIG. 2C for OR gate C is more appropriate to FPLA circuitry than the standard notation shown in FIG. 2B. The same format is followed in FIG. 2C as in FIG. 1C except that each circled intersection between line OC and a line LCJ for gate C in its unprogrammed state represents the coupling of line OC to line LCJ by way of fusible link FCJ and the emitter and base of transistor QCJ in the manner shown in FIG. 2A.
The general approach followed in FPLA design is to form products through AND gates and then form sums of the products through OR gates. Generally, each product is the product of selected opposite polarities of the data supplied to the AND gates. In some situations it is desirable to operate with NAND gates instead of AND gates or with NOR gates instead of OR gates. One conventional way to achieve this is to simply invert the output of each AND or OR gate.
The FPLA devices designated by product numbers 82S102/82S103, 82S100/82S101, and 82S104/82S105 and made by Signetics Corporation, Sunnyvale, Calif., follow the foregoing approach in their logic structure. The Signetics 82S102/103 and 82S100/101 are described in Signetics Bipolar & MOS Memory Data Manual, Signetics Corp., March 1978, pp. 146-155 and 163-166. The circuitry for the Signetics 82S104/105 is described by R. Cline in "A Single-Chip Sequential Logic Element," 1978 IEEE Int'l Solid-State Circuits Conference Digest of Technical Papers, 15-17 February 1978, pp 204-5. FIGS. 3-5 illustrate the unprogrammed FPLA circuitries for these devices using the simplified notation described above, but with all nodal dots omitted for clarity.
The Signetics 82S102/103 which is shown in FIG. 3 transmits input data received at 16 fixed input terminals I0-I15 to 16 inverter pairs NP0-NP15 which supply the true input data and its complement on 32 lines LA0-LA31. For example, the true data from pin I0 is provided to line LA0 from the leading inverter of inverter pair NP0 while the complement of the true data is provided to line LA1 from the trailing inverter of pair NP0. The data on lines LA0-LA31 is NANDed by a programmable logic array 20 of nine NAND gates AN0-AN8 each configured as in FIG. 1A, with a suitable inverter. The data from NAND array 20 is supplied to the first input elements in array 22 consisting of nine exclusive OR gates X0-X8 whose second input elements are each connected to ground through corresponding fusible links. Exclusive OR array 22 provides a capability to selectively invert the polarity of the data from NAND array 20. The output data from gates X0-X8 is transmitted through nine controllable output buffers BB0-BB8 to nine fixed output terminals B0-B8. Output buffers BB0-BB8 are enabled or disabled as a group through a common control line LE.
The Signetics 82S100/101 which is shown in FIG. 4 receives input data at fixed input pins I0-I15. As in the Signetics 82S102/103, the true input data and its complement are provided on lines LA0-LA31 from inverter pairs NP0-NP15. The data on lines LA0-LA31 is ANDed by a programmable logic array 30 of 48 AND gates A0-A47 each configured as in FIG. 1A. The data from AND array 30 is then ORed by a programmable logic array 32 of eight OR gates C0-C7 each configured as in FIG. 2A.
The data from OR array 32 is coupled to an array 34 of eight exclusive OR gates X0-X7 (configured in the same way as exclusive OR array 22 of the Signetics 82S102/103) to selectively generate either the true data from gates C0-C7 or its complement, depending on how the fusible links for grounding the second input elements of gates X0-X7 are programmed. Likewise eight output buffers BB0-BB7 on eight lines LY0-LY7 are controlled in the same manner as in the Signetics 82S102/103 to permit or inhibit the transmission of output data from gates X0-X7 to eight fixed output terminals B0-B7.
The Signetics 82S104/105 which is shown in FIG. 5 likewise transmits the true input data received at fixed input pins I0-I15 and its complement to lines LA0-LA31 by way of inverter pairs NP0-NP15. In addition, internal data is provided on 13 lines LA32-LA44. The data on lines LA0-LA44 is ANDed by programmable logic array 30 of AND gates A0-A47 each configured as in FIG. 1A. A programmable NOR loop 36, consisting of an OR gate CW configured as in FIG. 2A and in series with an inverter NW, feeds logic data complementary to that provided from AND gates A0-A47 back into them along line LA44. The data from AND array 30 is also ORed by a programmable logic array 38 of 28 OR gates H0-H27 each configured as in FIG. 2A.
The data from OR array 38 is provided to the S and R synchronous data input terminals of 14 RS flip-flops RS0-RS13 to provide a capability for on-chip data storage. Flip-flops RS0-RS13 can all be asynchronously preset as a group to a logical "1" state through a common control line LPE. The preset capability can be permanently disabled by blowing a suitable fusible link. Output data from the Q output terminals of flip-flops RS0-RS7 is provided on eight lines LZ0-LZ7 to eight fixed output terminals F0-F7 through eight controllable output buffers BF0-BF7. Buffers BF0-BF7 can all be permanently enabled by leaving the aforementioned fusible link intact. If this fuse is blown, buffers BF0-BF7 can be controlled through line LPE to permit or inhibit data transmission to pins F0-F7. Data from the Q output terminals of flip-flops RS8-RS13 is fed back on lines LU0-LU5 to AND array 30. In particular, the true data and its complement are provided through six inverter pairs NP16-NP21 to lines LA32-LA43.
The foregoing Signetics devices were among the first FPLA's in the semiconductor industry. However, they lack certain capabilities that will be advantageous in some future operations. For example, only the Signetics 82S104/105 has any internal feedback capability and that is somewhat limited. The output pins in all of these devices are fixed. None of the output pins can be temporarily or permanently employed for receiving circuit input data so as to provide greater input/output flexibility in some applications.
J. M. Birkner et al. in U.S. Pat. No. 4,124,899, "Programmable Array Logic Circuit" disclose various FPLA devices generally made by Monolithic Memories, Inc., Sunnyvale, Calif., and generally described further in Bipolar LSI Data Book, Monolithic Memories, Inc., 1978, pp 6-1-6-32. Birkner et al. disclose a few of the features not available in the foregoing Signetics devices. For example, Birkner et al. disclose feedback from non-programmable OR gates into a programmable AND array. Birkner et al. also disclose circuit terminals controlled by on-chip programmable control logic as either input pins or output pins.
However, Birkner et al. disclose no device comparable to the Signetics 82S102/103. None of the devices disclosed by Birkner et al. utilizes a field programmable OR array. Although Birkner et al. do disclose flip-flops for storing data supplied from OR gates, these flip-flops are D-type only and therefore of limited capability. None of the flip-flops have a preset or a reset capability. The capability to feed output data from the flip-flops back into them can only occur through an internally gated path and, consequently, it is not possible to load the flip-flops directly via any of the controllable input/output pins.